dbroqua/gh60_backlit
dbroqua/gh60_backlit
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gh60_backlit/gh60_backlit.kicad_pcb

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Initial commit with first design
2017-10-25 22:55:00 +02:00
(kicad_pcb (version 4) (host pcbnew 4.0.7+dfsg1-1)
(general
(links 29)
(no_connects 0)
Increased GND areas
2017-10-25 23:20:46 +02:00
(area 69.724999 99.024999 150.875001 114.875001)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(thickness 1.6)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(drawings 12)
(tracks 53)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(zones 0)
Increased GND areas
2017-10-25 23:20:46 +02:00
(modules 13)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(nets 7)
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(page A4)
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(net 1 LROW1)
(net 2 LCOL1)
(net 3 GND)
(net 4 VCC)
(net 5 GPIO2)
(net 6 "Net-(L1-Pad1)")
(net_class Default "This is the default net class."
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(add_net GPIO2)
(add_net LCOL1)
(add_net LROW1)
(add_net "Net-(L1-Pad1)")
(add_net VCC)
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Increased GND areas
2017-10-25 23:20:46 +02:00
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Initial commit with first design
2017-10-25 22:55:00 +02:00
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(fp_line (start 2.4 -2) (end -2.4 -2) (layer B.SilkS) (width 0.15))
(fp_line (start 2.4 2) (end 2.4 -2) (layer B.SilkS) (width 0.15))
(fp_line (start -2.4 2) (end 2.4 2) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.525 0 180) (size 1.5 3.6) (layers B.Cu B.Paste B.Mask)
(net 6 "Net-(L1-Pad1)"))
(pad 2 smd rect (at 1.525 0 180) (size 1.5 3.6) (layers B.Cu B.Paste B.Mask)
(net 1 LROW1))
)
Increased GND areas
2017-10-25 23:20:46 +02:00
(module Footprint:SOT-23-5 (layer B.Cu) (tedit 59F0FEE1) (tstamp 59F0FC65)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(at 139.4 110.8 270)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(descr "5-pin SOT23 package")
(tags SOT-23-5)
(path /59F0E2DC)
(attr smd)
Increased GND areas
2017-10-25 23:20:46 +02:00
(fp_text reference U1 (at 2.5908 -1.2573 360) (layer B.SilkS) hide
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PAM2804 (at -0.05 -2.35 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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(fp_circle (center -0.3 1.7) (end -0.2 1.7) (layer B.SilkS) (width 0.15))
(fp_line (start 0.25 1.45) (end -0.25 1.45) (layer B.SilkS) (width 0.15))
(fp_line (start 0.25 -1.45) (end 0.25 1.45) (layer B.SilkS) (width 0.15))
(fp_line (start -0.25 -1.45) (end 0.25 -1.45) (layer B.SilkS) (width 0.15))
(fp_line (start -0.25 1.45) (end -0.25 -1.45) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0.95 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
(net 5 GPIO2))
(pad 2 smd rect (at -1.1 0 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad 3 smd rect (at -1.1 -0.95 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
(net 6 "Net-(L1-Pad1)"))
(pad 4 smd rect (at 1.1 -0.95 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
(net 4 VCC))
(pad 5 smd rect (at 1.1 0.95 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
(net 2 LCOL1))
(model TO_SOT_Packages_SMD.3dshapes/SOT-23-5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F63C) (tstamp 59F10A7B)
(at 71.8 106.8)
(path /59F0F91D)
(fp_text reference 5_PIN_HEADER0 (at 0 7.62) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.25)))
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(fp_text value 5_PIN_HEADER (at 0 -7.62) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.25)))
)
(pad 5 thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 1 LROW1))
(pad 4 thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 1 LROW1))
(pad 1 thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 1 LROW1))
(pad 2 thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 1 LROW1))
(pad 3 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 1 LROW1))
)
(module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F638) (tstamp 59F10A84)
(at 90.85 106.8)
(path /59F0F4BC)
(fp_text reference 5_PIN_HEADER1 (at 0 7.62) (layer F.SilkS) hide
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(fp_text value 5_PIN_HEADER (at 0 -7.62) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.25)))
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(pad 5 thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
(pad 4 thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
(pad 1 thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
(pad 2 thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
(pad 3 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
)
(module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F630) (tstamp 59F10A8D)
(at 109.9 106.8)
(path /59F0F224)
(fp_text reference 5_PIN_HEADER2 (at 0 7.62) (layer F.SilkS) hide
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(fp_text value 5_PIN_HEADER (at 0 -7.62) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.25)))
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(pad 5 thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
(pad 4 thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
(pad 1 thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
(pad 2 thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
(pad 3 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 2 LCOL1))
)
(module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F60B) (tstamp 59F10A96)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(at 129 106.8 180)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(path /59F0EDCC)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(fp_text reference 5_PIN_HEADER3 (at 0 7.62 180) (layer F.SilkS) hide
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.25)))
)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(fp_text value 5_PIN_HEADER (at 0 -7.62 180) (layer F.Fab) hide
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.25)))
)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 5 thru_hole circle (at 0 5.08 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 2 LCOL1))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 4 thru_hole circle (at 0 2.54 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 2 LCOL1))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 1 thru_hole circle (at 0 -5.08 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 3 GND))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 2 thru_hole circle (at 0 -2.54 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 2 LCOL1))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 3 thru_hole circle (at 0 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 2 LCOL1))
)
(module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F5FC) (tstamp 59F10A9F)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(at 148 106.8 180)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(path /59F0E9FC)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(fp_text reference 5_PIN_HEADER4 (at 0 7.62 180) (layer F.SilkS) hide
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.25)))
)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(fp_text value 5_PIN_HEADER (at 0 -7.62 180) (layer F.Fab) hide
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.25)))
)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 5 thru_hole circle (at 0 5.08 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at 0 2.54 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask))
(pad 1 thru_hole circle (at 0 -5.08 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 4 VCC))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 2 thru_hole circle (at 0 -2.54 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 5 GPIO2))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 3 thru_hole circle (at 0 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask))
Initial commit with first design
2017-10-25 22:55:00 +02:00
)
(module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 58AA84A8) (tstamp 59F11764)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(at 143.9 110.7 90)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(descr "Capacitor SMD 0805, hand soldering")
(tags "capacitor 0805")
(path /59F0E39F)
(attr smd)
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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(fp_line (start -2.25 0.88) (end -2.25 -0.87) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.25 -0.87) (end 2.25 0.88) (layer B.CrtYd) (width 0.05))
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(pad 1 smd rect (at -1.25 0 90) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 4 VCC))
(pad 2 smd rect (at 1.25 0 90) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 58AA84A8) (tstamp 59F11769)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(at 134.1 104.3 270)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(descr "Capacitor SMD 0805, hand soldering")
(tags "capacitor 0805")
(path /59F0E3FF)
(attr smd)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(fp_text reference C2 (at 0 1.75 270) (layer B.SilkS)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(fp_text value 10uF (at 0 -1.75 270) (layer B.Fab)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(fp_text user %R (at 0 1.75 270) (layer B.Fab)
Initial commit with first design
2017-10-25 22:55:00 +02:00
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(fp_line (start 2.25 -0.87) (end -2.25 -0.87) (layer B.CrtYd) (width 0.05))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 1 smd rect (at -1.25 0 270) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 1 LROW1))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(pad 2 smd rect (at 1.25 0 270) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 3 GND))
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0805_HandSoldering (layer B.Cu) (tedit 58E0A804) (tstamp 59F1176E)
Increased GND areas
2017-10-25 23:20:46 +02:00
(at 134.2 110.5 90)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(descr "Resistor SMD 0805, hand soldering")
(tags "resistor 0805")
(path /59F0E43C)
(attr smd)
Increased GND areas
2017-10-25 23:20:46 +02:00
(fp_text reference R1 (at 0 1.7 90) (layer B.SilkS)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Increased GND areas
2017-10-25 23:20:46 +02:00
(fp_text value R (at 0 -1.75 90) (layer B.Fab)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Increased GND areas
2017-10-25 23:20:46 +02:00
(fp_text user %R (at 0 0 90) (layer B.Fab)
Initial commit with first design
2017-10-25 22:55:00 +02:00
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Increased GND areas
2017-10-25 23:20:46 +02:00
(pad 1 smd rect (at -1.35 0 90) (size 1.5 1.3) (layers B.Cu B.Paste B.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 2 LCOL1))
Increased GND areas
2017-10-25 23:20:46 +02:00
(pad 2 smd rect (at 1.35 0 90) (size 1.5 1.3) (layers B.Cu B.Paste B.Mask)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(net 3 GND))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Increased GND areas
2017-10-25 23:20:46 +02:00
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(xy 0.034304 -5.461) (xy 0.278585 -5.460888)) (layer F.SilkS) (width 0.01))
)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(gr_text o (at 73.9 101.2) (layer B.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
)
Increased GND areas
2017-10-25 23:20:46 +02:00
(gr_text "GH60\nBacklit\nrev. A" (at 81 107.2) (layer B.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
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(gr_line (start 150.8 112.8) (end 150.8 101.1) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 148.8 99.1) (end 71.8 99.1) (angle 90) (layer Edge.Cuts) (width 0.15))
Initial commit with first design
2017-10-25 22:55:00 +02:00
(gr_line (start 71.8 114.8) (end 148.8 114.8) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 71.8 112.8) (end 71.8 114.8) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 148.8 112.8) (end 150.8 112.8) (angle 90) (layer Edge.Cuts) (width 0.15))
Increased GND areas
2017-10-25 23:20:46 +02:00
(gr_arc (start 148.8 101.1) (end 148.8 99.1) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 71.8 101.1) (end 69.8 101.1) (angle 90) (layer Edge.Cuts) (width 0.15))
Initial commit with first design
2017-10-25 22:55:00 +02:00
(dimension 19.05 (width 0.3) (layer Cmts.User)
(gr_text "19.050 mm" (at 81.325 119.6) (layer Cmts.User)
(effects (font (size 1.5 1.5) (thickness 0.3)))
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(feature1 (pts (xy 90.85 106.8) (xy 90.85 120.95)))
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(crossbar (pts (xy 71.8 118.25) (xy 90.85 118.25)))
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(gr_line (start 71.8 106.8) (end 71.8 111.8) (angle 90) (layer Cmts.User) (width 0.2))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(segment (start 134.1 103.05) (end 134.1 102.4) (width 0.25) (layer B.Cu) (net 1) (status C00000))
(segment (start 134.1 102.4) (end 131.7 100) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F1CB78) (status 400000))
(segment (start 73.52 100) (end 71.8 101.72) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F1CB7B) (status 800000))
(segment (start 131.7 100) (end 73.52 100) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F1CB79))
(segment (start 134.05 103) (end 134.1 103.05) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F195CE))
(segment (start 134.1 102.95) (end 137.425 102.95) (width 0.25) (layer B.Cu) (net 1))
(segment (start 137.425 102.95) (end 138.075 103.6) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F195B1))
(segment (start 71.8 101.72) (end 71.8 103) (width 0.25) (layer B.Cu) (net 1))
(segment (start 71.8 103) (end 71.8 104.26) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F195CC))
Initial commit with first design
2017-10-25 22:55:00 +02:00
(segment (start 71.8 104.26) (end 71.8 106.8) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F11820))
(segment (start 71.8 106.8) (end 71.8 109.34) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F11821))
(segment (start 71.8 109.34) (end 71.8 111.88) (width 0.25) (layer B.Cu) (net 1) (tstamp 59F11822))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(segment (start 112.3 100.450002) (end 109.9 100.450002) (width 0.25) (layer B.Cu) (net 2))
(segment (start 109.9 100.450002) (end 109.9 101.72) (width 0.25) (layer B.Cu) (net 2) (tstamp 59F1CB8D) (status 800000))
(segment (start 109.9 101.72) (end 109.9 100.9) (width 0.25) (layer B.Cu) (net 2) (status C00000))
(segment (start 129 100.5) (end 129 101.72) (width 0.25) (layer B.Cu) (net 2) (tstamp 59F1CB87) (status 800000))
(segment (start 128.950002 100.450002) (end 129 100.5) (width 0.25) (layer B.Cu) (net 2) (tstamp 59F1CB84))
(segment (start 112.3 100.450002) (end 128.950002 100.450002) (width 0.25) (layer B.Cu) (net 2) (tstamp 59F1CB8B))
(segment (start 134.2 111.85) (end 138.4 111.85) (width 0.25) (layer B.Cu) (net 2))
(segment (start 138.4 111.85) (end 138.45 111.9) (width 0.25) (layer B.Cu) (net 2) (tstamp 59F19639))
(segment (start 129 106.8) (end 129 109.34) (width 0.25) (layer F.Cu) (net 2))
(segment (start 129 104.26) (end 129 106.8) (width 0.25) (layer F.Cu) (net 2))
(segment (start 134.2 111.85) (end 131.51 111.85) (width 0.25) (layer B.Cu) (net 2))
(segment (start 131.51 111.85) (end 129 109.34) (width 0.25) (layer B.Cu) (net 2) (tstamp 59F19575))
Increased GND areas
2017-10-25 23:20:46 +02:00
(segment (start 134.25 111.9) (end 134.2 111.85) (width 0.25) (layer B.Cu) (net 2) (tstamp 59F0FEB7))
(segment (start 109.9 106.8) (end 90.85 106.8) (width 0.25) (layer F.Cu) (net 2))
(segment (start 109.9 109.34) (end 109.9 111.88) (width 0.25) (layer F.Cu) (net 2))
(segment (start 109.9 106.8) (end 109.9 109.34) (width 0.25) (layer F.Cu) (net 2))
(segment (start 109.9 104.26) (end 109.9 106.8) (width 0.25) (layer F.Cu) (net 2))
(segment (start 90.85 111.88) (end 90.85 109.34) (width 0.25) (layer F.Cu) (net 2))
(segment (start 90.85 106.8) (end 90.85 109.34) (width 0.25) (layer F.Cu) (net 2))
(segment (start 90.85 104.26) (end 90.85 106.8) (width 0.25) (layer F.Cu) (net 2))
(segment (start 109.9 106.8) (end 128.95 106.8) (width 0.25) (layer F.Cu) (net 2))
(segment (start 90.85 101.72) (end 90.85 104.26) (width 0.25) (layer F.Cu) (net 2))
Initial commit with first design
2017-10-25 22:55:00 +02:00
(segment (start 109.9 101.72) (end 109.9 104.26) (width 0.25) (layer F.Cu) (net 2))
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
(segment (start 139.4 109.7) (end 139.4 107.3) (width 0.25) (layer B.Cu) (net 3))
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(segment (start 144.25 109) (end 144.3 109.05) (width 0.25) (layer B.Cu) (net 3) (tstamp 59F118A3))
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(segment (start 143.85 111.9) (end 143.9 111.95) (width 0.25) (layer B.Cu) (net 4) (tstamp 59F1963D))
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(segment (start 143.97 111.88) (end 143.9 111.95) (width 0.25) (layer B.Cu) (net 4) (tstamp 59F19616))
(segment (start 143.85 111.9) (end 143.9 111.95) (width 0.25) (layer B.Cu) (net 4) (tstamp 59F19613))
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(segment (start 138.45 110.8) (end 138.5 110.8) (width 0.25) (layer B.Cu) (net 5) (tstamp 59F19632))
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(segment (start 145.8 110.8) (end 146.3 110.8) (width 0.25) (layer B.Cu) (net 5) (tstamp 59F1960D))
(segment (start 145.3 110.8) (end 145.8 110.8) (width 0.25) (layer B.Cu) (net 5) (tstamp 59F1960C))
(segment (start 138.5 110.8) (end 145.3 110.8) (width 0.25) (layer B.Cu) (net 5) (tstamp 59F19635))
(segment (start 147.76 109.34) (end 148 109.34) (width 0.25) (layer B.Cu) (net 5) (tstamp 59F1960F))
(segment (start 141.125 103.6) (end 141.125 108.925) (width 0.25) (layer B.Cu) (net 6))
(segment (start 141.125 108.925) (end 140.35 109.7) (width 0.25) (layer B.Cu) (net 6) (tstamp 59F19640))
Initial commit with first design
2017-10-25 22:55:00 +02:00
Increased GND areas
2017-10-25 23:20:46 +02:00
(zone (net 3) (net_name GND) (layer F.Cu) (tstamp 59F0FD8D) (hatch edge 0.508)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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Increased GND areas
2017-10-25 23:20:46 +02:00
(xy 150.8 114.8) (xy 69.8 114.8) (xy 69.8 99.1) (xy 150.8 99.1)
Initial commit with first design
2017-10-25 22:55:00 +02:00
)
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Increased GND areas
2017-10-25 23:20:46 +02:00
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(xy 108.597932 112.748371) (xy 109.029357 113.180551) (xy 109.59333 113.414733) (xy 110.203991 113.415265) (xy 110.768371 113.182068)
Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
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Increased GND areas
2017-10-25 23:20:46 +02:00
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Initial commit with first design
2017-10-25 22:55:00 +02:00
)
)
)
Increased GND areas
2017-10-25 23:20:46 +02:00
(zone (net 3) (net_name GND) (layer B.Cu) (tstamp 59F0FD8D) (hatch edge 0.508)
Initial commit with first design
2017-10-25 22:55:00 +02:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
Increased GND areas
2017-10-25 23:20:46 +02:00
(xy 150.8 114.8) (xy 69.8 114.8) (xy 69.8 99.1) (xy 150.8 99.1)
Initial commit with first design
2017-10-25 22:55:00 +02:00
)
)
(filled_polygon
(pts
Increased GND areas
2017-10-25 23:20:46 +02:00
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Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
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Increased GND areas
2017-10-25 23:20:46 +02:00
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Fixed bug on wiring Rotated for pin header with GND and VCC.
2017-10-26 13:50:53 +02:00
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Initial commit with first design
2017-10-25 22:55:00 +02:00
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