diff --git a/Previews/BACK.png b/Previews/BACK.png
new file mode 100644
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diff --git a/Previews/FRONT.png b/Previews/FRONT.png
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diff --git a/gh60_backlit.kicad_pcb b/gh60_backlit.kicad_pcb
new file mode 100644
index 0000000..d969ef5
--- /dev/null
+++ b/gh60_backlit.kicad_pcb
@@ -0,0 +1,615 @@
+(kicad_pcb (version 4) (host pcbnew 4.0.7+dfsg1-1)
+
+  (general
+    (links 29)
+    (no_connects 0)
+    (area 69.724999 99.724999 150.875001 114.875001)
+    (thickness 1.6)
+    (drawings 10)
+    (tracks 72)
+    (zones 0)
+    (modules 10)
+    (nets 7)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (segment_width 0.2)
+    (edge_width 0.15)
+    (via_size 0.6)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.2)
+    (aux_axis_origin 0 0)
+    (grid_origin 71.8 106.8)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x00030_80000001)
+      (usegerberextensions false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15)
+      (hpglpenoverlay 2)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 LROW1)
+  (net 2 LCOL1)
+  (net 3 GND)
+  (net 4 VCC)
+  (net 5 GPIO2)
+  (net 6 "Net-(L1-Pad1)")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.6)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net GND)
+    (add_net GPIO2)
+    (add_net LCOL1)
+    (add_net LROW1)
+    (add_net "Net-(L1-Pad1)")
+    (add_net VCC)
+  )
+
+  (module Footprint:Inductor_Bourn_4mmx4mm (layer B.Cu) (tedit 56EAD789) (tstamp 59F0FC4D)
+    (at 139.6 103.6 180)
+    (path /59F0E354)
+    (fp_text reference L1 (at 0.1778 -2.5654 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uH (at 0 2.794 180) (layer Dwgs.User)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -2.4 -2) (end -2.4 2) (layer B.SilkS) (width 0.15))
+    (fp_line (start 2.4 -2) (end -2.4 -2) (layer B.SilkS) (width 0.15))
+    (fp_line (start 2.4 2) (end 2.4 -2) (layer B.SilkS) (width 0.15))
+    (fp_line (start -2.4 2) (end 2.4 2) (layer B.SilkS) (width 0.15))
+    (pad 1 smd rect (at -1.525 0 180) (size 1.5 3.6) (layers B.Cu B.Paste B.Mask)
+      (net 6 "Net-(L1-Pad1)"))
+    (pad 2 smd rect (at 1.525 0 180) (size 1.5 3.6) (layers B.Cu B.Paste B.Mask)
+      (net 1 LROW1))
+  )
+
+  (module Footprint:SOT-23-5 (layer B.Cu) (tedit 571FCFCA) (tstamp 59F0FC65)
+    (at 138.8 110.8 270)
+    (descr "5-pin SOT23 package")
+    (tags SOT-23-5)
+    (path /59F0E2DC)
+    (attr smd)
+    (fp_text reference U1 (at 2.5908 -1.2573 360) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value PAM2804 (at -0.05 -2.35 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_circle (center -0.3 1.7) (end -0.2 1.7) (layer B.SilkS) (width 0.15))
+    (fp_line (start 0.25 1.45) (end -0.25 1.45) (layer B.SilkS) (width 0.15))
+    (fp_line (start 0.25 -1.45) (end 0.25 1.45) (layer B.SilkS) (width 0.15))
+    (fp_line (start -0.25 -1.45) (end 0.25 -1.45) (layer B.SilkS) (width 0.15))
+    (fp_line (start -0.25 1.45) (end -0.25 -1.45) (layer B.SilkS) (width 0.15))
+    (pad 1 smd rect (at -1.1 0.95 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
+      (net 5 GPIO2))
+    (pad 2 smd rect (at -1.1 0 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (pad 3 smd rect (at -1.1 -0.95 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
+      (net 6 "Net-(L1-Pad1)"))
+    (pad 4 smd rect (at 1.1 -0.95 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
+      (net 4 VCC))
+    (pad 5 smd rect (at 1.1 0.95 270) (size 1.06 0.65) (layers B.Cu B.Paste B.Mask)
+      (net 2 LCOL1))
+    (model TO_SOT_Packages_SMD.3dshapes/SOT-23-5.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F63C) (tstamp 59F10A7B)
+    (at 71.8 106.8)
+    (path /59F0F91D)
+    (fp_text reference 5_PIN_HEADER0 (at 0 7.62) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (fp_text value 5_PIN_HEADER (at 0 -7.62) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (pad 5 thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 1 LROW1))
+    (pad 4 thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 1 LROW1))
+    (pad 1 thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 1 LROW1))
+    (pad 2 thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 1 LROW1))
+    (pad 3 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 1 LROW1))
+  )
+
+  (module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F638) (tstamp 59F10A84)
+    (at 90.85 106.8)
+    (path /59F0F4BC)
+    (fp_text reference 5_PIN_HEADER1 (at 0 7.62) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (fp_text value 5_PIN_HEADER (at 0 -7.62) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (pad 5 thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 4 thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 1 thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 2 thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 3 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+  )
+
+  (module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F630) (tstamp 59F10A8D)
+    (at 109.9 106.8)
+    (path /59F0F224)
+    (fp_text reference 5_PIN_HEADER2 (at 0 7.62) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (fp_text value 5_PIN_HEADER (at 0 -7.62) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (pad 5 thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 4 thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 1 thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 2 thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 3 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+  )
+
+  (module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F60B) (tstamp 59F10A96)
+    (at 128.95 106.8)
+    (path /59F0EDCC)
+    (fp_text reference 5_PIN_HEADER3 (at 0 7.62) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (fp_text value 5_PIN_HEADER (at 0 -7.62) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (pad 5 thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 4 thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 1 thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 3 GND))
+    (pad 2 thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+    (pad 3 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 LCOL1))
+  )
+
+  (module Footprint:5PIN_HEADER (layer F.Cu) (tedit 59F0F5FC) (tstamp 59F10A9F)
+    (at 148 106.8)
+    (path /59F0E9FC)
+    (fp_text reference 5_PIN_HEADER4 (at 0 7.62) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (fp_text value 5_PIN_HEADER (at 0 -7.62) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.25)))
+    )
+    (pad 5 thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask))
+    (pad 4 thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask))
+    (pad 1 thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 4 VCC))
+    (pad 2 thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 5 GPIO2))
+    (pad 3 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask))
+  )
+
+  (module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 58AA84A8) (tstamp 59F11764)
+    (at 144.3 107.8 90)
+    (descr "Capacitor SMD 0805, hand soldering")
+    (tags "capacitor 0805")
+    (path /59F0E39F)
+    (attr smd)
+    (fp_text reference C1 (at 0 1.75 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 10uF (at 0 -1.75 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 1.75 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -1 -0.62) (end -1 0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 -0.62) (end -1 -0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.62) (end 1 -0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.62) (end 1 0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.25 0.88) (end 2.25 0.88) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.25 0.88) (end -2.25 -0.87) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 2.25 -0.87) (end 2.25 0.88) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 2.25 -0.87) (end -2.25 -0.87) (layer B.CrtYd) (width 0.05))
+    (pad 1 smd rect (at -1.25 0 90) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
+      (net 4 VCC))
+    (pad 2 smd rect (at 1.25 0 90) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (model Capacitors_SMD.3dshapes/C_0805.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 58AA84A8) (tstamp 59F11769)
+    (at 134.1 103.9 90)
+    (descr "Capacitor SMD 0805, hand soldering")
+    (tags "capacitor 0805")
+    (path /59F0E3FF)
+    (attr smd)
+    (fp_text reference C2 (at 0 1.75 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 10uF (at 0 -1.75 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 1.75 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -1 -0.62) (end -1 0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 -0.62) (end -1 -0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.62) (end 1 -0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.62) (end 1 0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.25 0.88) (end 2.25 0.88) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.25 0.88) (end -2.25 -0.87) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 2.25 -0.87) (end 2.25 0.88) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 2.25 -0.87) (end -2.25 -0.87) (layer B.CrtYd) (width 0.05))
+    (pad 1 smd rect (at -1.25 0 90) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
+      (net 1 LROW1))
+    (pad 2 smd rect (at 1.25 0 90) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (model Capacitors_SMD.3dshapes/C_0805.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistors_SMD:R_0805_HandSoldering (layer B.Cu) (tedit 58E0A804) (tstamp 59F1176E)
+    (at 134.4 109.4)
+    (descr "Resistor SMD 0805, hand soldering")
+    (tags "resistor 0805")
+    (path /59F0E43C)
+    (attr smd)
+    (fp_text reference R1 (at 0 1.7) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value R (at 0 -1.75) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.075)) (justify mirror))
+    )
+    (fp_line (start -1 -0.62) (end -1 0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 -0.62) (end -1 -0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.62) (end 1 -0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.62) (end 1 0.62) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.6 -0.88) (end -0.6 -0.88) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.6 0.88) (end 0.6 0.88) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.35 0.9) (end 2.35 0.9) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.35 0.9) (end -2.35 -0.9) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 2.35 -0.9) (end 2.35 0.9) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 2.35 -0.9) (end -2.35 -0.9) (layer B.CrtYd) (width 0.05))
+    (pad 1 smd rect (at -1.35 0) (size 1.5 1.3) (layers B.Cu B.Paste B.Mask)
+      (net 2 LCOL1))
+    (pad 2 smd rect (at 1.35 0) (size 1.5 1.3) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0805.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_line (start 69.8 101.8) (end 69.8 112.8) (angle 90) (layer Edge.Cuts) (width 0.15))
+  (gr_line (start 148.8 99.8) (end 71.8 99.8) (angle 90) (layer Edge.Cuts) (width 0.15))
+  (gr_line (start 150.8 112.8) (end 150.8 101.8) (angle 90) (layer Edge.Cuts) (width 0.15))
+  (gr_line (start 71.8 114.8) (end 148.8 114.8) (angle 90) (layer Edge.Cuts) (width 0.15))
+  (gr_arc (start 71.8 112.8) (end 71.8 114.8) (angle 90) (layer Edge.Cuts) (width 0.15))
+  (gr_arc (start 148.8 112.8) (end 150.8 112.8) (angle 90) (layer Edge.Cuts) (width 0.15))
+  (gr_arc (start 148.8 101.8) (end 148.8 99.8) (angle 90) (layer Edge.Cuts) (width 0.15))
+  (gr_arc (start 71.8 101.8) (end 69.8 101.8) (angle 90) (layer Edge.Cuts) (width 0.15))
+  (dimension 19.05 (width 0.3) (layer Cmts.User)
+    (gr_text "19.050 mm" (at 81.325 119.6) (layer Cmts.User)
+      (effects (font (size 1.5 1.5) (thickness 0.3)))
+    )
+    (feature1 (pts (xy 90.85 106.8) (xy 90.85 120.95)))
+    (feature2 (pts (xy 71.8 106.8) (xy 71.8 120.95)))
+    (crossbar (pts (xy 71.8 118.25) (xy 90.85 118.25)))
+    (arrow1a (pts (xy 90.85 118.25) (xy 89.723496 118.836421)))
+    (arrow1b (pts (xy 90.85 118.25) (xy 89.723496 117.663579)))
+    (arrow2a (pts (xy 71.8 118.25) (xy 72.926504 118.836421)))
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diff --git a/gh60_backlit.pro b/gh60_backlit.pro
new file mode 100644
index 0000000..c18565b
--- /dev/null
+++ b/gh60_backlit.pro
@@ -0,0 +1,32 @@
+update=Wed 25 Oct 2017 09:15:25 PM CEST
+version=1
+last_client=kicad
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[general]
+version=1
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=/home/dbroqua/Projects/dbroqua/kicad_parts/kicad_parts
diff --git a/gh60_backlit.sch b/gh60_backlit.sch
new file mode 100644
index 0000000..98625d6
--- /dev/null
+++ b/gh60_backlit.sch
@@ -0,0 +1,363 @@
+EESchema Schematic File Version 2
+LIBS:kicad_parts
+LIBS:gh60_backlit-cache
+EELAYER 25 0
+EELAYER END
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+encoding utf-8
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+Text GLabel 1550 1150 2    60   Input ~ 0
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+Text GLabel 1550 1250 2    60   Input ~ 0
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+Wire Wire Line
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+Wire Wire Line
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