90 lines
3 KiB
Diff
90 lines
3 KiB
Diff
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
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index 661c5a38f..a25d61d54 100644
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--- a/drivers/gpio/gpio-mvebu.c
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+++ b/drivers/gpio/gpio-mvebu.c
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@@ -38,6 +38,7 @@
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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+#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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@@ -133,7 +134,7 @@ struct mvebu_gpio_chip {
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struct regmap *regs;
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u32 offset;
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struct regmap *percpu_regs;
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- int irqbase;
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+ int bank_irq[4];
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struct irq_domain *domain;
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int soc_variant;
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@@ -608,6 +609,33 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
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chained_irq_exit(chip, desc);
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}
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+/*
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+ * Set interrupt number "irq" in the GPIO as a wake-up source.
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+ * While system is running, all registered GPIO interrupts need to have
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+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
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+ * need to have wake-up enabled.
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+ * @param irq interrupt source number
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+ * @param enable enable as wake-up if equal to non-zero
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+ * @return This function returns 0 on success.
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+ */
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+static int mvebu_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
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+{
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+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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+ struct mvebu_gpio_chip *mvchip = gc->private;
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+ int irq;
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+ int bank;
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+
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+ bank = d->hwirq % 8;
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+ irq = mvchip->bank_irq[bank];
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+
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+ if (enable)
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+ enable_irq_wake(irq);
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+ else
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+ disable_irq_wake(irq);
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+
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+ return 0;
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+}
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+
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/*
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* Functions implementing the pwm_chip methods
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*/
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@@ -1277,7 +1305,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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err = irq_alloc_domain_generic_chips(
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mvchip->domain, ngpios, 2, np->name, handle_level_irq,
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- IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
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+ IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, IRQ_GC_INIT_NESTED_LOCK);
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if (err) {
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dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
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mvchip->chip.label);
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@@ -1295,6 +1323,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
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ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
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ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
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+ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
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+ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
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ct->chip.name = mvchip->chip.label;
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ct = &gc->chip_types[1];
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@@ -1303,6 +1333,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
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ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
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ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
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+ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
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+ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
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ct->handler = handle_edge_irq;
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ct->chip.name = mvchip->chip.label;
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@@ -1318,6 +1350,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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continue;
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irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
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mvchip);
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+ mvchip->bank_irq[i] = irq;
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}
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/* Some MVEBU SoCs have simple PWM support for GPIO lines */
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